In many memory systems, such as in synchronous dynamic random access memory (SDRAM), it may be advantageous to have a cloned delay line to shift commands in the system clock time domain to a delay locked loop (DLL) time domain. The DLL time domain represents the time domain for various clock and control signals internal to a memory. To save layout area, this cloned delay line may be a combined command line, that is, it may carry both read and write commands. The read and write commands may be extended over multiple clock cycles in order to reduce the power requirements of the memory system. The extended read and write commands may be separated at the output of the DLL for subsequent use by components of the memory system. The layout and power conservation advantages of the above configuration may be negatively impacted by the inability to separate read and write commands properly when a read command is followed closely by a write command in memory systems with tight timing specifications.